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• W2118744911 abstract "We review trends in interconnect bandwidth requirements for multiprocessor systems and technologies proposed to meet these requirements. The benefits and costs of core-based optoelectronic chips are discussed using CMOS-SEED implementations of the WARRP network router as a case study. Results indicate that transistor density and on-chip clock rates of optoelectronic core-based designs can be reduced by as much as 40% and 30%, respectively, but aggregate off-chip bandwidth can be increased by as much as an order of magnitude as compared to all-electronic chip designs." @default.
• W2118744911 created "2016-06-24" @default.
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• W2118744911 date "1999-01-01" @default.
• W2118744911 modified "2023-09-24" @default.
• W2118744911 title "Design issues for core-based optoelectronic chips: a case study of the WARRP network router" @default.
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• W2118744911 doi "https://doi.org/10.1109/2944.778317" @default.
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