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- W2118799833 abstract "As packet-switching interconnection networks replace buses and dedicated wires to become the standard on-chip interconnection fabric, reducing their power consumption has been identified to be a major design challenge. Network topologies have high impact on network power consumption. Technology scaling is another important factor that affects network power, since each new technology changes semiconductor physical properties. These two aspects need to be considered synergistically. We characterize the impact of process technologies on network energy for a range of topologies, starting from 2-dimensional meshes/tori, to variants of meshes/tori that incorporate higher dimensions, multiple hierarchies and express channels. We present a method which uses an analytical model to predict the most energy-efficient topology based on network size and architecture parameters for future technologies. Our model is validated against cycle-accurate network power simulation and shown to arrive at the same predictions. We also show how our method can be applied to actual parallel benchmarks with a case study. We see this work as a starting point for defining a roadmap of future on-chip networks." @default.
- W2118799833 created "2016-06-24" @default.
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- W2118799833 date "2005-04-01" @default.
- W2118799833 modified "2023-09-24" @default.
- W2118799833 title "A Technology-Aware and Energy-Oriented Topology Exploration for On-Chip Networks" @default.
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- W2118799833 doi "https://doi.org/10.1109/date.2005.40" @default.
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