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• W2118961575 abstract "Networks-on-chip (NoCs) represent a promising solution to complex on-chip communication problems. The NoC communication architectures considered so far are based on either completely regular or fully customized topologies. In this paper, we present a methodology to automatically synthesize an architecture which is neither regular nor fully customized. Instead, the communication architecture we propose is a superposition of a few long-range links and a standard mesh network. The few application-specific long-range links we insert significantly increase the critical traffic workload at which the network transitions from a free to a congested state. This way, we can exploit the benefits offered by both complete regularity and partial topology customization. Indeed, our experimental results demonstrate a significant reduction in the average packet latency and a major improvement in the achievable network through with minimal impact on network topology" @default.
• W2118961575 created "2016-06-24" @default.
• W2118961575 creator A5036227385 @default.
• W2118961575 creator A5084255924 @default.
• W2118961575 date "2006-07-01" @default.
• W2118961575 modified "2023-10-02" @default.
• W2118961575 title "It's a small world after all: NoC performance optimization via long-range link insertion" @default.
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• W2118961575 doi "https://doi.org/10.1109/tvlsi.2006.878263" @default.
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