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- W2119219787 abstract "In this letter, a 78 ~ 102 GHz front-end receiver designed in 90 nm CMOS technology is presented. It consists of an ultra-wideband low-noise amplifier, a subharmonic mixer, and an IF buffer. This receiver has a peak gain of 11.8 dB at 94 GHz with the noise figure of 13.4 dB. The measured input-referred 1 dB compression point is -14.5 dBm and the total power dissipation is 18.6 mW. The chip size is 680 × 1020 μm <sup xmlns:mml=http://www.w3.org/1998/Math/MathML xmlns:xlink=http://www.w3.org/1999/xlink>2</sup> ." @default.
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- W2119219787 date "2011-09-01" @default.
- W2119219787 modified "2023-10-18" @default.
- W2119219787 title "A 78 $sim$ 102 GHz Front-End Receiver in 90 nm CMOS Technology" @default.
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- W2119219787 doi "https://doi.org/10.1109/lmwc.2011.2162940" @default.
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