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• W2119540583 abstract "An 8-bit successive approximation (SA) analog-to- digital converter (ADC) in 0.18 mum CMOS dedicated for energy-limited applications is presented. The SA ADC achieves a wide effective resolution bandwidth (ERBW) by applying only one bootstrapped switch, thereby preserving the desired low power characteristic. Measurement results show that at a supply voltage of 0.9 V and an output rate of 200 kS/s, the SA ADC performs a peak signal-to-noise-and-distortion ratio of 47.4 dB and an ERBW up to its Nyquist bandwidth (100 kHz). It consumes 2.47 muW in the test, corresponding to a figure of merit of 65 f J/conversion-step." @default.
• W2119540583 created "2016-06-24" @default.
• W2119540583 creator A5013515932 @default.
• W2119540583 creator A5078005376 @default.
• W2119540583 date "2007-10-01" @default.
• W2119540583 modified "2023-10-01" @default.
• W2119540583 title "A 65-fJ/Conversion-Step 0.9-V 200-kS/s Rail-to-Rail 8-bit Successive Approximation ADC" @default.
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• W2119540583 doi "https://doi.org/10.1109/jssc.2007.905237" @default.
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