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- W2119740948 abstract "This paper presents a new mechanism for power analysis and reduction that exploits the hierarchical nature of circuits. A number of mechanisms have been proposed for power reduction, but they do not offer solutions in all cases. An activity-based reduction technique is presented where the clock is turned off for entire modules or sub-modules hierarchically when that portion of the circuit is not in use. Behavioral constraints are used to determine when a portion of the circuit is in use. The method shown is a top-down approach independent of the technology used during fabrication of the chip. Experimental results indicate that this method will result in a considerable reduction in power." @default.
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- W2119740948 date "2002-12-23" @default.
- W2119740948 modified "2023-09-25" @default.
- W2119740948 title "A hierarchical approach for power reduction in VLSI chips" @default.
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- W2119740948 doi "https://doi.org/10.1109/glsv.1996.497617" @default.
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