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- W2119866965 abstract "A leakage compensation technique is presented to compensate the on-chip loop filter leakage for phase-locked loops in 65-nm complementary metal-oxide-semiconductor technology. Using the leakage compensation technique, the measured root-mean-square jitter is reduced to 3.10 ps when the output frequency is 950 MHz. This chip consumes 10 mW, and the active area is 0.14 mm <sup xmlns:mml=http://www.w3.org/1998/Math/MathML xmlns:xlink=http://www.w3.org/1999/xlink>2</sup> ." @default.
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- W2119866965 date "2009-07-01" @default.
- W2119866965 modified "2023-09-25" @default.
- W2119866965 title "A Leakage-Compensated PLL in 65-nm CMOS Technology" @default.
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- W2119866965 doi "https://doi.org/10.1109/tcsii.2009.2020948" @default.
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