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• W2120461663 abstract "This technology utilizes multiple localized ion implantations directly into semi-insulating GaAs substrates, with unimplanted areas providing isolation between circuit elements. This approach allows for high yield, high density circuits, with optimization of various types of devices (e.g., GaAs MESFETs, high-speed Schottky-barrier diodes, etc.) made possible by optimizing the implantation profile for each type of device. The application of this fabrication technology for high-speed, ultra low power digital integrated circuits using a new circuit approach called Schottky diode-FET logic (SDFL) is described. Experimental GaAS SDFL logic ICs with LSI/VLSI compatible power levels (200-500 /spl mu/W/gate) and circuit densities (<10/SUP -3/ mm/SUP 2//gate) have been fabricated." @default.
• W2120461663 created "2016-06-24" @default.
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• W2120461663 date "1978-08-01" @default.
• W2120461663 modified "2023-09-24" @default.
• W2120461663 title "Planar GaAs IC technology: Applications for digital LSI" @default.
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• W2120461663 doi "https://doi.org/10.1109/jssc.1978.1051071" @default.
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