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- W2120589360 abstract "In order to reduce the power dissipation correlative with redundant states in sequential circuits and the redundant leap of the lock, low power design of decimal counter is proposed in this paper. PSPICE simulation shows the design has correct logic function and low power dissipation." @default.
- W2120589360 created "2016-06-24" @default.
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- W2120589360 date "2011-04-01" @default.
- W2120589360 modified "2023-09-24" @default.
- W2120589360 title "Decimal counter based on redundancy-restraining technique" @default.
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- W2120589360 doi "https://doi.org/10.1109/iceice.2011.5777273" @default.
- W2120589360 hasPublicationYear "2011" @default.
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