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• W2120611134 abstract "A novel stacked microvia technology is being developed by the Packaging Research Center (PRC) at the Georgia Institute of Technology for system-on-a package (SOP) applications. This ultra-high density build-up multilayer technology uses low cost processes to fabricate stacked microvias of non-conformal copper studs with uniform height on organic printed wiring boards. This process involves the use of copper panel plating and selective etch back using a protective or barrier layer to protect the underlying circuit traces. We have termed this new process PES (Panel Plating Etch Stud). Stacked via technology offers higher wiring capability and improved performance compared with conventional conformal microvias used for high density interconnect (HDI) boards. This paper will review the current statns of via filling technologies for stacked vias and descrihe the new P'ES process along with preliminary results. In addition, the PRC is also developing ultra fme circuit lines and spaces on printed circuit boards. The use of stacked vias along with ultra fme line technology will dramatically reduce size and increase performance of electronic systems." @default.
• W2120611134 created "2016-06-24" @default.
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• W2120611134 date "2004-06-22" @default.
• W2120611134 modified "2023-09-26" @default.
• W2120611134 title "A novel technology for stacking microvias on printed wiring board" @default.
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• W2120611134 doi "https://doi.org/10.1109/ectc.2003.1216434" @default.
• W2120611134 hasPublicationYear "2004" @default.
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