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- W2120738260 abstract "Three-dimensional stacked integrated circuits (3D-SICs) implemented with through-silicon vias (TSVs) and micro-bumps open new horizons for faster, smaller, and more energy-efficient chips. As all micro-electronic structures, these 3D chips and their interconnects need to be tested for manufacturing defects. Previously, we defined, implemented, and automated a 3D-DfT (Design-for-Test) architecture that provides modular test access for 3D-SICs containing monolithic logic dies in a single-tower stack. However, the logic dies comprising a 3D-SIC typically are complex System-on-Chip (SoC) designs that include embedded intellectual property (IP) cores, wrapped for modular test. Also, multi-tower 3D-SICs have started to emerge. In this paper, our existing 3D-DfT architecture is extended with support for wrapped embedded IP cores and multi-tower stacks and its implementation is automated with industrial electronic design automation (EDA) tools." @default.
- W2120738260 created "2016-06-24" @default.
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- W2120738260 date "2013-05-01" @default.
- W2120738260 modified "2023-10-16" @default.
- W2120738260 title "Automated DfT insertion and test generation for 3D-SICs with embedded cores and multiple towers" @default.
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- W2120738260 doi "https://doi.org/10.1109/ets.2013.6569350" @default.
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