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- W2121450829 abstract "To be able to manage increasing chip complexity, the re-use of already designed functional modules has become a standard design practise in state-of-the-art ASIC design. In this paper, the impact of these re-used modules on the testability of the entire chip has been investigated. For this purpose, a complex telecom ASIC with re-used interface logic running at 155 MHz, used in an ATM (Asynchronous Transfer Mode) application, has been studied. The single stuck-at fault coverage for the random logic, obtained with combinational ATPG, has been increased by 21% by performing some minor design modifications and using sequential ATPG. In addition, it has been shown that with respect to I/sub DDQ/ testing, automatic test vector generation has to be preferred over fault grading hand-written functional test vector sets. With I/sub DDQ/ test vector generation 95% fault coverage has been obtained with only 66% of the flip-flops being scannable." @default.
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- W2121450829 date "2002-11-19" @default.
- W2121450829 modified "2023-09-26" @default.
- W2121450829 title "Coping with re-usability using sequential ATPG: a practical case study" @default.
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- W2121450829 doi "https://doi.org/10.1109/test.1995.529840" @default.
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