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- W2121686345 abstract "This brief presents an electrostatic discharge (ESD)-protected receiver front-end for wireless communications around 24 GHz. A Π-type input matching network incorporating two split ESD capacitances and an on-chip inductor is constructed to realize the source impedance transformation for high gain, good input matching, and only slightly degraded noise figure (NF). The measured results show that the front-end has an input return loss of less than -12 dB, a 36-dB voltage gain, a 6.8-dB NF, and a 2-dBm output CP <sub xmlns:mml=http://www.w3.org/1998/Math/MathML xmlns:xlink=http://www.w3.org/1999/xlink>1dB</sub> . The chip, fabricated in 0.13-μm RF CMOS process, has a protection level equivalent to ±2-kV human body model ESD and consumes 40 mA from a 1.2-V supply with a total area of 1 × 0.8 mm <sup xmlns:mml=http://www.w3.org/1998/Math/MathML xmlns:xlink=http://www.w3.org/1999/xlink>2</sup> ." @default.
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- W2121686345 date "2011-08-01" @default.
- W2121686345 modified "2023-10-17" @default.
- W2121686345 title "Design of 24-GHz High-Gain Receiver Front-End Utilizing ESD-Split Input Matching Network" @default.
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- W2121686345 doi "https://doi.org/10.1109/tcsii.2011.2158723" @default.
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