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- W2122039306 abstract "High performance, high density scaled MOS processes have been developed by reducing parasitic lead capacitances and resistances through the use of MoSi 2 gates and polyimide as interlevel dielectric insulator. The self-aligned gates were passivated using dual layer of doped oxide and DuPont PI2545 polyamic resin 1.7 micron thick reducing interlevel capacitance to 2.66×10-9farads/cm2, half that of conventional doped oxide. The speed power products estimated from 25 stage ring oscillator with 2 micron gates on 600A gate oxides show minimum delays of 500 psec/gate and minimum speed power product of 120 femto joules at lower currents." @default.
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- W2122039306 date "1979-01-01" @default.
- W2122039306 modified "2023-09-27" @default.
- W2122039306 title "High performance, high density MOS process using polyimide interlevel insulation" @default.
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- W2122039306 doi "https://doi.org/10.1109/iedm.1979.189657" @default.
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