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• W2122144558 abstract "This paper presents a complete design tool which performs automatic behavioral synthesis of asynchronous circuits (resource sharing, scheduling and binding).The tool targets a traditional control-datapath-style template architecture. Within the limitations set by this template architecture it is possible to optimize for area (which is our main focus) or for speed. This is done by simply using different cost functions.Input to the tool is a behavioral description in the Haste language, and output from the tool is a Haste program describing the synthesized implementation consisting of adatapath and a controller. The tool may be seen as an add-on to the Haste/TiDE tool flow, and it can be used to automatically optimize parts of a design and to quickly explore alternative optimizations. The paper outlines the design flow, explains key elements of the design tool, and presents a number of benchmark results." @default.
• W2122144558 created "2016-06-24" @default.
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• W2122144558 date "2009-05-01" @default.
• W2122144558 modified "2023-09-28" @default.
• W2122144558 title "A Behavioral Synthesis Frontend to the Haste/TiDE Design Flow" @default.
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• W2122144558 doi "https://doi.org/10.1109/async.2009.10" @default.
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