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• W2122652610 abstract "A 5-bit 500-MS/s time-domain flash ADC is presented. The proposed ADC consists of a reference resistor ladder, two voltage-to-time converter arrays, a time-domain comparator array and a digital encoder without sample-and-hold. In order to achieve low-power consumption with high conversion-speed and to enhance design reusability in terms of a highly digital implementation with more regular mask patterns, the time-domain comparison is devised in the flash ADC. The prototype has been implemented and fabricated in a standard 0.18 μm CMOS technology and occupies 0.132 mm 2 without pads. The measured SNDR and SFDR up to the Nyquist frequency are 26.6 dB and 35.1 dB, respectively. And the peak DNL and INL are measured as 0.43 LSB and 0.58 LSB, respectively. The prototype consumes 8 mW with a 1.8-V supply voltage." @default.
• W2122652610 created "2016-06-24" @default.
• W2122652610 creator A5003439616 @default.
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• W2122652610 date "2012-12-01" @default.
• W2122652610 modified "2023-09-27" @default.
• W2122652610 title "A 5-BIT 500-MS/S FLASH ADC USING TIME-DOMAIN COMPARISON" @default.
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• W2122652610 doi "https://doi.org/10.1142/s0218126612400233" @default.
• W2122652610 hasPublicationYear "2012" @default.
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