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• W2123080193 abstract "A pipelined /spl Delta/-/spl Sigma/ analog-to-digital-converter architecture is described that incorporates the high speed of pipelined converters and the high resolution of oversampling quantization. A prototype, containing both modulation and decimation circuits on a single chip, is implemented using a 1.2-/spl mu/m commercial CMOS process. It uses charge-coupled-device elements to perform pipelined analog operations. It exhibits a maximum data rate of 18 MHz, a signal-to-noise ratio of 74 dB, spurious-free dynamic range of 78 dB, differential nonlinearity of <0.15 LSB at 13 bits, and power dissipation of 324 mW." @default.
• W2123080193 created "2016-06-24" @default.
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• W2123080193 date "1999-01-01" @default.
• W2123080193 modified "2023-10-03" @default.
• W2123080193 title "A Nyquist-rate pipelined oversampling A/D converter" @default.
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• W2123080193 doi "https://doi.org/10.1109/4.808902" @default.
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