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- W2123129670 abstract "A novel SRAM architecture with a high density cell in low supply voltage operation is proposed. A self-write-back sense amplifier realizes cell failure rate improvement by more than two orders of magnitude at 0.6 V. A cascaded bit line scheme saves additional process cost for hierarchical bit line layer. A test chip with 256 kb SRAM utilizing 0.495 um <sup xmlns:mml=http://www.w3.org/1998/Math/MathML xmlns:xlink=http://www.w3.org/1999/xlink>2</sup> cell in 65 nm CMOS technology demonstrated 0.7 V single supply operation." @default.
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- W2123129670 date "2008-06-01" @default.
- W2123129670 modified "2023-09-27" @default.
- W2123129670 title "A 0.7V single-supply SRAM with 0.495um<sup>2</sup> cell in 65nm technology utilizing self-write-back sense amplifier and cascaded bit line scheme" @default.
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- W2123129670 doi "https://doi.org/10.1109/vlsic.2008.4585946" @default.
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