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• W2124266507 abstract "We investigate the gate-delay-fault testability properties of multilevel, multiplexor-based logic circuits. Based on this investigation, we describe a procedure for synthesizing gate-delay-fault testable multilevel circuits. The procedure involves the construction of a multilevel circuit from a general, unordered Binary Decision Diagram (BDD) by replacing vertices of the BDD with multiplexors. The procedure relies on the following result derived in this article: If the multilevel circuit constructed from the BDD is initially fully single stuck-at fault testable, or made fully single stuck-at fault testable by redundancy removal, then it is completely robustly gate-delay-fault testable. Once the initial gate-delay-fault testable circuit has been obtained, constrained algebraic factorization is used to improve the area and performance characteristics without compromising testability. Unlike previous techniques for synthesizing robustly gate-delay-fault testable circuits, this procedure can be used to synthesize fully testable circuits directly from nonflattenable, logic-level implementations." @default.
• W2124266507 created "2016-06-24" @default.
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• W2124266507 date "2005-08-24" @default.
• W2124266507 modified "2023-09-23" @default.
• W2124266507 title "Gate-Delay-Fault Testability Properties of Multiplexor-Based Networks" @default.
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• W2124266507 doi "https://doi.org/10.1109/test.1991.519755" @default.
• W2124266507 hasPublicationYear "2005" @default.
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