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- W2125261494 abstract "An 8.5-Gb/s single-chip optoelectronic integrated circuit (OEIC) for short-distance optical communications is realized in a 0.13- <formula formulatype=inline xmlns:mml=http://www.w3.org/1998/Math/MathML xmlns:xlink=http://www.w3.org/1999/xlink> <tex Notation=TeX>$mu$</tex></formula> m CMOS process. The OEIC consists of an on-chip silicon photodiode, a transimpedance amplifier with modified regulated cascode input configuration, an adaptive equalizer based upon slope-detection algorithm, and a limiting amplifier with merged negative impedance circuits. The proposed slope-detection adaptive equalizer compensates the limited bandwidth and the temperature variation of the integrated silicon photodiode. Measured results demonstrate 120-dB <formula formulatype=inline xmlns:mml=http://www.w3.org/1998/Math/MathML xmlns:xlink=http://www.w3.org/1999/xlink><tex Notation=TeX>$Omega$</tex></formula> transimpedance gain, 5.9-GHz bandwidth, <formula formulatype=inline xmlns:mml=http://www.w3.org/1998/Math/MathML xmlns:xlink=http://www.w3.org/1999/xlink><tex Notation=TeX>${-}$</tex> </formula> 3.2-dBm optical sensitivity for 10 <formula formulatype=inline xmlns:mml=http://www.w3.org/1998/Math/MathML xmlns:xlink=http://www.w3.org/1999/xlink> <tex Notation=TeX>$^{-12}$</tex></formula> BER, and 47-mW power dissipation from a single 1.5-V supply. The OEIC chip core occupies the area of 0.1 mm <formula formulatype=inline xmlns:mml=http://www.w3.org/1998/Math/MathML xmlns:xlink=http://www.w3.org/1999/xlink><tex Notation=TeX>$^{2}$</tex></formula> ." @default.
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- W2125261494 date "2010-12-01" @default.
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- W2125261494 title "An 8.5-Gb/s Fully Integrated CMOS Optoelectronic Receiver Using Slope-Detection Adaptive Equalizer" @default.
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