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- W2125667788 abstract "In this paper, we show how to use Verilog HDL along with PLI (Programming Language Interface) to model asynchronous circuits at the behavioral level by implementing CSP (Communicating Sequential Processes) language constructs. Channels and communicating actions are modeled in Verilog HDL as abstract actions." @default.
- W2125667788 created "2016-06-24" @default.
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- W2125667788 date "2003-06-02" @default.
- W2125667788 modified "2023-10-16" @default.
- W2125667788 title "Verilog HDL, powered by PLI" @default.
- W2125667788 cites W4211008702 @default.
- W2125667788 doi "https://doi.org/10.1145/775832.775917" @default.
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