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- W2125744510 abstract "Microprocessors have been used in wide-ranged applications. During the execution of instructions, instruction decoding is a major task for identifying instructions and generating control signals for data-paths. By exploiting program behaviors, we propose a novel instruction-decoding approach for power minimization. Using the proposed instruction-decoding structure, we present a partitioning method that decomposes the instruction-decoding circuit into two sub-circuits according to the execution frequencies of instructions. Using our proposed decoding structure, only one sub-circuit will be activated when executing an instruction. Experimental results have demonstrated that our proposed approach achieves on an average of 26.71% and 15.69% power reductions for the instruction decoder and the control unit, respectively." @default.
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- W2125744510 date "2004-02-16" @default.
- W2125744510 modified "2023-09-22" @default.
- W2125744510 title "Decomposition of instruction decoder for low power design" @default.
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- W2125744510 doi "https://doi.org/10.5555/968878.968993" @default.
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