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- W2125887976 abstract "Transistors in aggressively scaled CMOS technologies have f <sub xmlns:mml=http://www.w3.org/1998/Math/MathML xmlns:xlink=http://www.w3.org/1999/xlink>T</sub> greater than 150 GHz, which exceeds requirements for most existing commercial applications below 10 GHz. Excess transistor performance can be traded-off for cost by designing out inductors. This paper presents a prototype which exploits the speed of transistors to design highly integrated broadband receiver front-ends. The inductor-less prototype operates from 2 to 5.8 GHz and dissipates 85 mW at 5 GHz while occupying 0.2 mm <sup xmlns:mml=http://www.w3.org/1998/Math/MathML xmlns:xlink=http://www.w3.org/1999/xlink>2</sup> active area. It provides 44 dB of gain, 3.4 dB double side band noise figure, 21 dBm in-band IIP3 in the highest gain mode and 15 dB input matching." @default.
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- W2125887976 date "2008-05-01" @default.
- W2125887976 modified "2023-10-18" @default.
- W2125887976 title "A Broadband Low-Cost Direct-Conversion Receiver Front-End in 90 nm CMOS" @default.
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- W2125887976 doi "https://doi.org/10.1109/jssc.2008.920358" @default.
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