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- W2126072301 abstract "In this paper we present a novel 1-bit full adder cell. The cell offer less power consumption in comparison with the conventional and current implementation of the full adder cell, especially at low voltages. All transitions are used for simulation to obtain the delay and the power consumption parameters. Simulation is improved in term of power consumption. The new full adder cell is simulated at 0.18_µm CMOS technology, using HSPICE." @default.
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- W2126072301 date "2010-06-01" @default.
- W2126072301 modified "2023-09-24" @default.
- W2126072301 title "A new low power full adder cell in CMOS inverter" @default.
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- W2126072301 doi "https://doi.org/10.1109/icias.2010.5716112" @default.
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