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- W2126259048 abstract "An ultra-compact three-stage amplifier is proposed by merging current buffer Miller compensation with parallel compensation, which achieves significant improvement in area efficiency without sacrificing the gain-bandwidth product (GBW) and power. Fabricated in 0.35 µm CMOS the amplifier measures 4.98 MHz GBW at 150 pF load while drawing 20 µA at 2 V. The entailed compensation capacitance is minimised to 1.5 pF and the chip size is merely 0.012 mm2." @default.
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- W2126259048 date "2012-01-01" @default.
- W2126259048 modified "2023-10-02" @default.
- W2126259048 title "Ultra-area-efficient three-stage amplifier using current buffer Miller compensation and parallel compensation" @default.
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- W2126259048 doi "https://doi.org/10.1049/el.2012.0711" @default.
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