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- W2127223876 abstract "Presented is a method for formal verification of pipelined processors with long instruction queues. The execution engine and the fetch engine (where the instruction queue is) are formally verified separately, after abstracting the other engine with a non-deterministic FSM derived from the high-level specification of that engine. Without the presented method, the monolithic formal verification of 9-stage, 9-wide VLIW processors--implementing many realistic and speculative features inspired by the Intel Itanium--scaled for models with 5 instruction-queue entries, but ran out of memory if the instruction queue was longer. The presented method resulted in 2 orders of magnitude speedup for the processor with 5 instruction-queue entries, and enabled scaling for designs with 64 instruction-queue entries." @default.
- W2127223876 created "2016-06-24" @default.
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- W2127223876 date "2004-04-26" @default.
- W2127223876 modified "2023-10-16" @default.
- W2127223876 title "Efficient formal verification of pipelined processors with instruction queues" @default.
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- W2127223876 doi "https://doi.org/10.1145/988952.988975" @default.
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