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• W2127315516 abstract "A high-speed 16-Mb DRAM chip with on-chip error-correcting code (ECC), which supports either 11/11 or 12/0 RAS/CAS addressing and operates on a 3.3- or 5-V power supply, is described. It can be packaged as a 2-Mb*8, 4-Mb*4, 8-Mb*2, or 16-Mb*1 DRAM, And is capable of operating in fast page mode, static column mode, or toggle mode. Speed and flexibility are achieved by a pipeline layout and on-chip SRAMs that buffer entire ECC words. The use of redundant word and bit lines in conjunction with the ECC produces a synergistic fault-tolerance effect.< <ETX xmlns:mml=http://www.w3.org/1998/Math/MathML xmlns:xlink=http://www.w3.org/1999/xlink>></ETX>" @default.
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• W2127315516 date "1990-01-01" @default.
• W2127315516 modified "2023-09-26" @default.
• W2127315516 title "A 50-ns 16-Mb DRAM with a 10-ns data rate and on-chip ECC" @default.
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• W2127315516 doi "https://doi.org/10.1109/4.62132" @default.
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