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- W2127601024 abstract "FPGAs are gradually becoming an essential flexible-digital solution for automotive and military applications, where operating at extreme ambient temperature conditions reaching 125°C are not uncommon. Operating FPGAs under such high-temperature environments require adequate timing margin to compensate potential delay increase, which worsens the performance of FPGAs. To minimize the performance degradation, we propose a thermal gradient aware clock skew scheduling technique which allocates temperature-adaptive timing margins considering worst case thermal gradients and junction temperature ranges of logic-paths in the design, instead of assigning a worst case timing margin to the entire design. The experimental results shows that our technique extends the operating ambient temperature range with an average about 20% performance improvement." @default.
- W2127601024 created "2016-06-24" @default.
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- W2127601024 date "2010-08-01" @default.
- W2127601024 modified "2023-10-16" @default.
- W2127601024 title "Thermal Gradient Aware Clock Skew Scheduling for FPGAs" @default.
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- W2127601024 doi "https://doi.org/10.1109/fpl.2010.29" @default.
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