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- W2127788323 abstract "Long ago predicted limits for the planar CMOS structure, Silicon (Si) materials, and optical lithography are now present and being addressed in present day 32 and 28nm technology logic nodes. However, as the market emphasis shifts from high performance computing to consumer mobile in the race to produce the next 15 billion intelligent, connected devices by 2015, new issues such as extreme low power constraints and low cost have now became a priority as the industry has hit a power supply 1V Wall [1] for logic technologies. This paper looks at the logic technology roadmap for the next 10 years with a new perspective. With power, cost, and System On a Chip (SOC) being the present day industry market drivers, do many of the projects started ~30 years ago to address scaling and fundamental limits to Si planar CMOS (e.g. Multigate MOSFETs, III-V materials, etc), still make sense today?" @default.
- W2127788323 created "2016-06-24" @default.
- W2127788323 creator A5022988277 @default.
- W2127788323 date "2010-01-01" @default.
- W2127788323 modified "2023-09-23" @default.
- W2127788323 title "Power, cost and circuit IP reuse: The real limiter to Moore's Law over the next 10 years" @default.
- W2127788323 cites W2002566635 @default.
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- W2127788323 doi "https://doi.org/10.1109/vtsa.2010.5488936" @default.
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