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- W2127843031 abstract "System-on-chip (SoC) designs suffer from the growing global interconnect delay as device density and chip area increase. Three-dimensional integrated circuits (3D ICs) have been proposed as a way to reduce global wire length. Despite this key advantage of 3D ICs, 3D designs must effectively address two critical issues: heat dissipation and manufacturing cost. In this paper, we propose a new methodology that explores the trade-off between performance and cost of a SoC design, while keeping maximum on-chip temperature at an acceptable level. We analyze the performance of two multimedia systems and describe the implications of scaling SoC designs to 3D." @default.
- W2127843031 created "2016-06-24" @default.
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- W2127843031 date "2005-07-27" @default.
- W2127843031 modified "2023-09-24" @default.
- W2127843031 title "Mapping System-on-Chip Designs from 2-D to 3-D ICs" @default.
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- W2127843031 doi "https://doi.org/10.1109/iscas.2005.1465243" @default.
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