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• W2128292496 abstract "A high performance 0.25 /spl mu/m CMOS process has been developed for fast static RAMs, featuring retrograde wells, shallow trench isolation with 0.55 /spl mu/m active pitch, a 55 /spl Aring/ nitrided gate oxide, 0.25 /spl mu/m polycide gate surface channel NMOS and PMOS transistors with drive currents of 630 and 300 /spl mu/A//spl mu/m respectively at an off-leakage of 10 pA//spl mu/m, overgated TFTs with an on/off ratio greater than 6/spl middot/10/sup 5/, stacked capacitors for improved SER, five levels of polysilicon planarized by chemical-mechanical polishing (CMP), with two self-aligned interpoly contacts and a tungsten interpoly plug (WIP) that connects 3 poly layers without parasitic diodes, 0.35 /spl mu/m contacts and a 0.625 /spl mu/m metal pitch. A split word-line bitcell was scaled to an area of 3.74 /spl mu/m/sup 2/ using 0.25 /spl mu/m design rules." @default.
• W2128292496 created "2016-06-24" @default.
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• W2128292496 date "2002-11-19" @default.
• W2128292496 modified "2023-09-28" @default.
• W2128292496 title "High performance 0.25 μm SRAM technology with tungsten interpoly plug" @default.
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• W2128292496 doi "https://doi.org/10.1109/iedm.1995.499368" @default.
• W2128292496 hasPublicationYear "2002" @default.
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