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• W2129020301 abstract "The design of embedded subthreshold SRAMs for a quality-scalable H.264 video decoder IP is presented in this paper. In addition to the conventional 7T SRAM bitcell, we adopted power-gating techniques and multi-output dynamic circuits in order to achieve a low VDD <sub xmlns:mml=http://www.w3.org/1998/Math/MathML xmlns:xlink=http://www.w3.org/1999/xlink>min</sub> , a small area overhead, and a higher operating speed. A 256 × 32 90-nm SRAM macro was designed for verifying the proposed design techniques. The H.264 IP provides energy-efficient scalable video decoding of 42.8 pJ/cycle for QCIF and 235 pJ/cycle for HD720 at 0.3 V and 0.7 V, respectively." @default.
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• W2129020301 date "2011-06-01" @default.
• W2129020301 modified "2023-09-26" @default.
• W2129020301 title "Design of Subthreshold SRAMs for Energy-Efficient Quality-Scalable Video Applications" @default.
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• W2129020301 doi "https://doi.org/10.1109/jetcas.2011.2158345" @default.
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