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- W2129057069 abstract "<para xmlns:mml=http://www.w3.org/1998/Math/MathML xmlns:xlink=http://www.w3.org/1999/xlink> A 12 bit 2.9 GS/s current-steering DAC implemented in 65 nm CMOS is presented, with an <formula formulatype=inline><tex Notation=TeX>$IM3 ≪ -60~{hbox {dBc}}$</tex></formula> beyond 1 GHz while driving a 50 <formula formulatype=inline><tex Notation=TeX>$Omega $</tex></formula> load with an output swing of 2.5 <formula formulatype=inline> <tex Notation=TeX>$V_{rm ppd}$</tex></formula> and dissipating a power of 188 mW. The SFDR measured at 2.9<formula formulatype=inline><tex Notation=TeX>$~$</tex> </formula>GS/s is better than 60 dB beyond 340 MHz while the SFDR measured at 1.6 GS/s is better than 60 dB beyond 440 MHz. The increase in performance at high-frequencies, compared to previously published results, is mainly obtained by adding local cascodes on top of the current-switches with “always-ON” biasing. </para>" @default.
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- W2129057069 date "2009-12-01" @default.
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- W2129057069 title "A 12 bit 2.9 GS/s DAC With IM3 $ ≪ -$60 dBc Beyond 1 GHz in 65 nm CMOS" @default.
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- W2129057069 doi "https://doi.org/10.1109/jssc.2009.2032624" @default.
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