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- W2129197150 abstract "A fully ion-implanted process allows high-density integration of NMOS, CMOS, and bipolar transistors for VLSI of analog-digital systems. Supply voltage can be 20 V. Thresholds are /spl plusmn/1.5 V for p- and n-channel enhancement transistors, respectively. Standard deviation per wafer is 15 mV for the NMOS threshold, while the NMOS gain constant is 30 /spl mu/AV/SUP -2/. The bipolar transistors have a low-resistance base contact. Current gain can be set independently. For current gain=90, the Early voltage if V/SUB A/=110 V. No epi layer, isolation diffusions, or channel stoppers are required. The mask count is 6 for structure definition plus 2 for the masking of implants. The process can be scaled along the learning curve of digital MOS VLSI." @default.
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- W2129197150 date "1979-04-01" @default.
- W2129197150 modified "2023-09-28" @default.
- W2129197150 title "A fully implanted NMOS, CMOS, bipolar technology for VLSI of analog-digital systems" @default.
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- W2129197150 doi "https://doi.org/10.1109/jssc.1979.1051180" @default.
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