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• W2129969303 abstract "Single BJT BiCMOS devices exhibit sequential behavior under transistor stuck-OPEN (s-OPEN) faults. In addition to the sequential behavior, delay faults are also present. Detection of s-OPEN faults exhibiting sequential behavior needs two-pattern or multipattern sequences, and delay faults are all the more difficult to detect. A new design for testability scheme is presented that uses only two extra transistors to improve the circuit testability regardless of timing skews/delays, glitches, or charge sharing among internal nodes. With this design, only a single vector is required to test for a fault instead of the two-pattern or multipattern sequences. The testable design scheme presented also avoids the requirement of generating tests for delay faults. >" @default.
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• W2129969303 date "1995-01-01" @default.
• W2129969303 modified "2023-09-27" @default.
• W2129969303 title "Testable design of BiCMOS circuits for stuck-open fault detection using single patterns" @default.
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• W2129969303 doi "https://doi.org/10.1109/4.400427" @default.
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