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• W2130324569 abstract "Performance degradation due to insertion of BIST logic into high-speed designs has been analyzed. A framework to introduce BIST into random logic circuits, without causing timing violations has been proposed. Various heuristics for selecting flip-flops for BIST have been developed and studied in detail. Experimental results indicate an improvement in performance while optimizing fault coverage and area overhead." @default.
• W2130324569 created "2016-06-24" @default.
• W2130324569 creator A5043018467 @default.
• W2130324569 creator A5055158645 @default.
• W2130324569 date "2002-11-19" @default.
• W2130324569 modified "2023-09-26" @default.
• W2130324569 title "Performance driven BIST technique for random logic" @default.
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• W2130324569 doi "https://doi.org/10.1109/test.1995.529880" @default.
• W2130324569 hasPublicationYear "2002" @default.
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