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• W2130342495 abstract "The impact of a high-k gate dielectric on the device and circuit performances of nanoscale double-gate (DG) FinFET CMOS technology is examined via physics-based device/circuit simulations. DG FinFETs are designed with high k at the high- performance 45-nm node of the 2005 Semiconductor Industry Association International Technology Roadmap for Semiconductors (ITRS; L <sub xmlns:mml=http://www.w3.org/1998/Math/MathML xmlns:xlink=http://www.w3.org/1999/xlink>g</sub> = 18 nm), and are compared with a pragmatic design in which the traditional SiON (or SiO <sub xmlns:mml=http://www.w3.org/1998/Math/MathML xmlns:xlink=http://www.w3.org/1999/xlink>2</sub> ) gate dielectric is retained and kept relatively thick to avoid excessive gate tunneling current. Whereas it is presumed that a high-k dielectric, if and when adequately integrated, will significantly enhance CMOS scalability and performance, we show that there are heretofore unacknowledged compromising effects associated with it that undermine this enhancement. In fact, our results show that for DG FinFET CMOS, a high-k gate dielectric actually undermines speed performance while giving little improvement in scalability relative to the pragmatic design, whereas the latter can be scaled, with good performance, to the end of the ITRS." @default.
• W2130342495 created "2016-06-24" @default.
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• W2130342495 date "2008-07-01" @default.
• W2130342495 modified "2023-09-23" @default.
• W2130342495 title "On the Suitability of a High-$k$ Gate Dielectric in Nanoscale FinFET CMOS Technology" @default.
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• W2130342495 doi "https://doi.org/10.1109/ted.2008.925161" @default.
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