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- W2130397798 abstract "A 20-MHz to 3-GHz wide-range multiphase delay-locked loop (DLL) has been realized in 90-nm CMOS technology. The proposed delay cell extends the operation frequency range. A scaling circuit is adopted to lower the large delay gain when the frequency of the input clock is low. The core area of this DLL is 0.005 mm <sup xmlns:mml=http://www.w3.org/1998/Math/MathML xmlns:xlink=http://www.w3.org/1999/xlink>2</sup> . The measured power consumption values are 0.4 and 3.6 mW for input clocks of 20 MHz and 3 GHz, respectively. The measured peak-to-peak and root-mean-square jitters are 2.3 and 16 ps at 3 GHz, respectively." @default.
- W2130397798 created "2016-06-24" @default.
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- W2130397798 date "2009-11-01" @default.
- W2130397798 modified "2023-09-23" @default.
- W2130397798 title "A 20-MHz to 3-GHz Wide-Range Multiphase Delay-Locked Loop" @default.
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- W2130397798 doi "https://doi.org/10.1109/tcsii.2009.2032477" @default.
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