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• W2130693213 abstract "A layout design algorithm for a variable-width inductor is proposed to minimize metal resistance. For a given chip area, the proposed algorithm can rapidly design metal widths of each coil in a planar inductor due to the analytical form. Two on-chip inductors with identical chip areas and inductance are fabricated to verify the proposed method in foundry 90-nm CMOS technology. Measurement results demonstrate that the improvement of metal resistance in the proposed device is approximately 19%. The results of this paper provide an effective algorithm to design a high-Q inductor for RFIC applications." @default.
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• W2130693213 date "2008-11-01" @default.
• W2130693213 modified "2023-09-25" @default.
• W2130693213 title "Analytical Design Algorithm of Planar Inductor Layout in CMOS Technology" @default.
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• W2130693213 doi "https://doi.org/10.1109/ted.2008.2004248" @default.
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