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- W2130757686 abstract "Parallel digital logarithmic (DIGILOG) coding of n-bit data is implemented in CMOS with n/4 gate delays and a compression to (log/sub 2/n+m-1) bits for m-bit relative accuracy. Multiplication becomes an addition of logarithms with two parallel adders of length (1+log/sub 2/n) and (m-1), respectively. Expansive decoding yields a 2n-bit product. The transistor count of a DIGILOG multiplier can be less than one quarter and the multiplication time can be less than one half in comparison with a Booth-Wallace multiplier. >" @default.
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- W2130757686 date "2002-12-09" @default.
- W2130757686 modified "2023-09-25" @default.
- W2130757686 title "Digital logarithmic CMOS multiplier for very-high-speed signal processing" @default.
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- W2130757686 doi "https://doi.org/10.1109/cicc.1991.164069" @default.
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