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- W2130921921 abstract "A distributed on-chip decoupling capacitor network is proposed in this paper. A system of distributed on-chip decoupling capacitors is shown to provide an efficient solution for providing the required on-chip decoupling capacitance under existing technology constraints. In a system of distributed on-chip decoupling capacitors, each capacitor is sized based on the parasitic impedance of the power distribution grid. Various tradeoffs in a system of distributed on-chip decoupling capacitors are also discussed. Related simulation results for typical values of on-chip parasitic resistance are also presented. The worst case error is 0.003% as compared to SPICE." @default.
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- W2130921921 date "2008-12-01" @default.
- W2130921921 modified "2023-10-18" @default.
- W2130921921 title "Efficient Distributed On-Chip Decoupling Capacitors for Nanoscale ICs" @default.
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- W2130921921 doi "https://doi.org/10.1109/tvlsi.2008.2001735" @default.
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