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- W2132016257 abstract "Two gated ring oscillators (GRO) act as the delay lines in an improved Vernier time-to-digital converter (TDC). The already small quantization noise of the standard Vernier TDC is further first-order shaped by the GRO operation. The TDC has been implemented in a 90nm CMOS technology and achieves a resolution better than 5ps for a signal bandwidth of 800kHz. The current consumption is 3mA from 1.2V when operating at 25MHz." @default.
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- W2132016257 date "2011-09-01" @default.
- W2132016257 modified "2023-10-17" @default.
- W2132016257 title "A 90nm CMOS gated-ring-oscillator-based Vernier time-to-digital converter for DPLLs" @default.
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- W2132016257 doi "https://doi.org/10.1109/esscirc.2011.6045006" @default.
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