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• W2132301251 abstract "The emergence of power as a first-class design constraint has fueled the proposal of a growing number of run-time power optimizations. Many of these optimizations trade-off power saving opportunity for a variable performance loss which depends on application characteristics and program phase. Furthermore, the potential benefits of these optimizations are sometimes non-additive, and it can be difficult to identify which combinations of these optimizations to apply. Trial-and-error approaches have been proposed to adaptively tune a processor. However, in a chip multiprocessor, the cost of individually configuring each core under a wide range of optimizations might be prohibitive under simple trial-and-error approaches." @default.
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• W2132301251 date "2008-10-25" @default.
• W2132301251 modified "2023-09-25" @default.
• W2132301251 title "Multi-optimization power management for chip multiprocessors" @default.
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• W2132301251 doi "https://doi.org/10.1145/1454115.1454141" @default.
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