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- W2132535970 abstract "This paper presents the design of parameterized fixed-point integer multiplication, squaring and fractional division units. The units are targeted at the Virtex-II family of FPGAs (field programmable gate arrays) from Xilinx and are based on the small 18X18-bit multiplier blocks. New partial product creation and summation techniques that exploit the low level primitives are used that achieve a 20% area and a 30% delay reduction for multiplication. A dedicated squaring component is presented that offers substantial area savings of up to 50%. The division component uses the multipliers for pre-scaling to reduce the delay and complexity of each minimally redundant radix-8 stage." @default.
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- W2132535970 date "2003-10-31" @default.
- W2132535970 modified "2023-09-25" @default.
- W2132535970 title "Improved small multiplier based multiplication, squaring and division" @default.
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- W2132535970 doi "https://doi.org/10.1109/fpga.2003.1227245" @default.
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