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- W2132653450 abstract "A high-performance implementation of the International Data Encryption Algorithm (IDEA) is presented in this paper. Using a novel bit-serial architecture to perform multiplication modulo 2/sup 16/+1, the implementation occupies a minimal amount of hardware. The bit-serial architecture enabled the algorithm to be deeply pipelined to achieve a system clock rate of 125 MHz on a Xilinx Virtex XCV300-6, delivering a throughput of 500 Mb/sec. With a XCV1000-6 device, the estimated performance is 2 Gb/sec, three orders of magnitude faster than a software implementation on a 450 MHz Intel Pentium II. This design is suitable for applications in on-line encryption for high-speed networks." @default.
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- W2132653450 date "2002-11-11" @default.
- W2132653450 modified "2023-09-27" @default.
- W2132653450 title "A bit-serial implementation of the international data encryption algorithm IDEA" @default.
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- W2132653450 doi "https://doi.org/10.1109/fpga.2000.903399" @default.
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