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- W2132881562 abstract "BIST is a viable approach to test today's digital systems. Constraints, such as power, noise, area overhead, and others, limit the possibilities of parallel BIST execution in complex VLSI devices. This paper presents a BIST scheduling process that takes into consideration such constraints, and introduces a new BIST control methodology, that implements the BIST schedule with a highly modular architecture. In fact, due to the uniformity of interface, the BIST control elements are independent of the BIST scheme used in the embedded blocks of a device. This BIST control architecture can provide block level diagnostic information.< <ETX xmlns:mml=http://www.w3.org/1998/Math/MathML xmlns:xlink=http://www.w3.org/1999/xlink>></ETX>" @default.
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- W2132881562 date "2002-12-31" @default.
- W2132881562 modified "2023-10-03" @default.
- W2132881562 title "A distributed BIST control scheme for complex VLSI devices" @default.
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- W2132881562 doi "https://doi.org/10.1109/vtest.1993.313316" @default.
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