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- W2132993912 abstract "Although state-of-the-art field-programmable gate arrays offer exciting new opportunities in exploring low-cost high-performance architectures for data-intensive scientific applications, they also present serious challenges. Multiprocessor-on-programmable-chip, which integrates software programmability and hardware reconfiguration, provides substantial flexibility that results in shorter design cycles, higher performance, and lower cost. In this article, we present an application-specific design methodology for multiprocessor-on-programmable-chip architectures that target applications involving large matrices and floating-point operations. Given an application with specific energy-performance and resource constraints, our methodology aims to customize the architecture to match the diverse computation and communication requirements of the application tasks. Graph-based analysis of the application drives system synthesis that employs a precharacterized, parameterized hardware component library of functional units. Extensive experimental results for three diverse applications are presented to demonstrate the efficacy of our design methodology." @default.
- W2132993912 created "2016-06-24" @default.
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- W2132993912 date "2011-10-01" @default.
- W2132993912 modified "2023-10-09" @default.
- W2132993912 title "Resource-constrained multiprocessor synthesis for floating-point applications on FPGAs" @default.
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- W2132993912 doi "https://doi.org/10.1145/2003695.2003701" @default.
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