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• W2133171792 abstract "Along with the progress of VLSI technology, buffer insertion plays an increasingly critical role on affecting circuit design and performance. Traditional buffer insertion algorithms are mostly net based and therefore often result in sub-optimal delay or unnecessary buffer expense due to the lack of global view. In this paper, we propose a novel path based buffer insertion scheme which can overcome the weakness of the net based approaches. We also discuss some potential difficulties of the path based buffer insertion approach and propose solutions to them. A fast estimation on buffered delay is employed to improve the solution quality. Gate sizing is also considered at the same time. Experimental results show that our method can efficiently reduce buffer/gate cost significantly (by 71% on average) when compared to traditional net based approaches. To the best of our knowledge, this is the first work on path based buffer insertion and simultaneous gate sizing." @default.
• W2133171792 created "2016-06-24" @default.
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• W2133171792 date "2005-01-01" @default.
• W2133171792 modified "2023-10-03" @default.
• W2133171792 title "Path based buffer insertion" @default.
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• W2133171792 doi "https://doi.org/10.1145/1065579.1065711" @default.
• W2133171792 hasPublicationYear "2005" @default.
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