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• W2133952327 abstract "New methods for automated visual recognition of metal interconnect technological layers of integrated circuits are presented. Image processing and analysis algorithms are used in these methods to extract interconnect structure locations and dimensions. Recognized structure data is used to recreate initial photolithographic mask data suitable for further analysis. Proposed methods were experimentaly tested and their precision was calculated from test results. To perform experimental testing, custom software was developed as a framework for this and future research. Methods proposed here are initial part of collection of methods suitable for complete chip topological structure extraction, including all layers. Ill. 4, bibl. 13 (in English; summaries in English, Russian and Lithuanian)." @default.
• W2133952327 created "2016-06-24" @default.
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• W2133952327 date "2008-10-20" @default.
• W2133952327 modified "2023-10-03" @default.
• W2133952327 title "Reverse engineering of CMOS integrated circuits" @default.
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• W2133952327 doi "https://doi.org/10.5755/j01.eee.88.8.11227" @default.
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