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• W2134346541 abstract "In this paper, we propose an efficient algorithm to reduce the voltage noises for on-chip power/ground (P/G) networks of VLSI. The new method is based on the sequence of linear programming (SLP) method as the optimization engine and a localized scheme via partitioning for dealing with large circuits. We show that by directly optimizing the decap area as the objective function and using the time-domain adjoint method, SLP can deliver much better quality than existing methods based on the merged time-domain adjoint method. The partitioning strategy further improves the scalability of the proposed algorithm and makes it efficient for large circuits. The resulting algorithm is general enough for any P/G network. Experimental results demonstrate the advantage of the proposed method over existing state-of-the-art methods in terms of solution quality at a mild computation cost increase." @default.
• W2134346541 created "2016-06-24" @default.
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• W2134346541 date "2006-04-07" @default.
• W2134346541 modified "2023-09-27" @default.
• W2134346541 title "Localized On-Chip Power Delivery Network Optimization via Sequence of Linear Programming" @default.
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• W2134346541 doi "https://doi.org/10.1109/isqed.2006.81" @default.
• W2134346541 hasPublicationYear "2006" @default.
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